MEDs Fabrication (MOSIS Rep)
From prototype to production, MOSIS is a design engineer's single source for a wide variety of semiconductor processes offered by major foundries.
Costs are kept low by combining designs from many customers into multi-project wafer (MPW) runs.
With prototype costs reduced, engineers can submit several variations of the same design to the same run, thus shortening time-to-market.
Final designs can then be submitted to MEDs/MOSIS for low- medium volume production or dedicated Engineering wafer runs (COT).
Technology descriptions, fabrication schedules, and vendor document access procedures for the IBM, TSMC, ON Semiconductor, austriamicrosystems, Globalfoundries, and Peregrine fabrication processes available through MOSIS.
| IBM Fabrication Processes The IBM fabrication processes available through MOSIS range from 45 nanometer to 0.25 µm in CMOS, and from 0.13 µm to 0.50 µm in SiGe BiCMOS. TSMC Fabrication Processes The TSMC fabrication processes available through MOSIS range from 40 nanometer to 0.35 µm. Low power, low voltage, and high voltage options are available in most of these technologies. ON Semiconductor Fabrication Processes The ON Semi CMOS processes available through MOSIS range from 0.35 µm to 0.7 µm. austriamicrosystems Fabrication Processes Processes offered by MOSIS through austriamicrosystems include 0.35 µm CMOS, high voltage CMOS, SiGe BiCMOS, and 0.18 µm CMOS and high voltage CMOS. Globalfoundries Fabrication Processes Processes offered by MOSIS through Globalfoundries include 65 nanometer. Tezzaron Fabrication Processes The Tezzaron fabrication processes available through MOSIS include two-tier 3DIC 130 nm CMOS. Peregrine Fabrication Processes The Peregrine fabrication processes available through MOSIS include both 0.50 µm SOS process (FC and FA), and the two versions of the 0.25 µm SOS process (GA and GC). |
For more information about these processes, please contact MEDs.
Credited to MOSIS